The present invention relates to techniques for testing programmable circuits, and more particularly, to techniques for automatically generating tests for programmable circuit using a connectivity graph.
Programmable logic circuits (PLDs) include logic elements, memory, and conductors that are programmably connected in an interconnect structure. The logic elements and the connections to the conductors can be programmed according a number of different designs.
After a PLD is manufactured, the logic elements, memory, and programmable connections in the interconnect structure are tested to ensure that they are operating properly. Tests are performed to detect the presence of any manufacturing detects in the programmable logic device (PLD).
It would be desirable to provide techniques for testing programmable circuits that reduce the time spent by engineers to perform the tests.